Opening. This role is responsible for developing and deploying robust layout methodologies that ensure high-quality, manufacturable designs. The ideal candidate will have a strong foundation in IC layout fundamentals and deep understanding of foundry design rules.
What you'll do
Intro.
- Demonstrate in-depth knowledge of IC layout principles including matching, symmetry, common-centroid, shielding, noise mitigation, EM/IR, ESD/latch-up awareness.
- Apply a comprehensive understanding of foundry DRC/LVS/ERC/ANT/DFM rules to ensure full compliance while optimizing manufacturability, performance, and yield.
- Perform and analyze sign-off checks: DRC/LVS/ERC/ANT/ESD/DFM; debug with schematic, design, and PD teams.
- Prepare release/tapeout packages: GDS/OASIS, LEF/DEF, abstracts, waiver documentation, ECO tracking, sign-off reports.
What you need
- Experience: 3–8+ years in IC Layout/Physical Design with successful tapeouts.
- EDA Tools: Cadence Virtuoso (L/XL/GXL), Innovus / Synopsys CC / ICC2; Mentor/Siemens Calibre (DRC/LVS/DFM).
- Foundries: Hands-on experience with TSMC/Samsung/UMC/GlobalFoundries PDKs.
- Strong English communication skills for technical communication.
