You are a visionary and highly accomplished digital design and verification engineer with over 15 years of impactful experience in ASIC development, large-scale system validation, and hardware emulation. As a Principal Engineer, you are recognized for your technical leadership, strategic thinking, and exceptional ability to architect, model, and validate complex mixed-signal SoC systems.
What you'll do
Providing technical leadership and architectural direction for the design and emulation of advanced mixed-signal SoCs, including next-generation SerDes PHY products.
Driving the development and integration of hardware emulation strategies on FPGA platforms (Zebu, HAPS).
Orchestrating the build and validation of system-level prototypes for industry-leading protocols (PCIE, Ethernet, USB, etc.), ensuring seamless integration with PHY builds.
What you need
15+ years of experience in ASIC design, verification, system validation, and technical leadership roles.
- Recognized expertise with hardware emulation platforms (Zebu, HAPS) and FPGA-based prototyping for signal PHY and back-to-back systems.
