You will work on Speed Adapter solutions that enable the most advanced system-level validation in the industry. The protocols are cutting edge, the customers are the ones defining the next generation of silicon, and what you build will directly determine whether their chip works when it comes back from the fab.
You will design and develop Speed Adapter solutions for PCIe Gen5/Gen6, CXL 2.0/3.x, UCIe, and AXI protocols that bridge real-world high-speed I/O with designs running on ZeBu emulation and HAPS prototyping platforms.
You will implement protocol logic and speed adaptation functionality on FPGA-based platforms, managing the translation layer between multi-gigabit real-world interfaces and reduced-speed DUTs.
You will develop and debug RTL, firmware, and system-level components across the full Speed Adapter stack, from transceiver configuration to protocol state machines to host integration.
You will collaborate with IP teams, emulation platform engineers, and prototyping teams to deliver integrated system-level validation solutions that customers can deploy in their labs.
You will build reference designs, example flows, and integration documentation that enable customers to connect their DUTs to real devices, testers, and hosts with minimal friction.
You will support customer escalations involving complex system-level issues, performing root-cause analysis across hardware, firmware, and protocol layers to deliver solutions that actually resolve the problem.
You will contribute to roadmap planning and feature definition for next-generation Speed Adapter products, including emerging protocols and differentiated capabilities not available from competitors.
You will enable top semiconductor and hyperscale customers to validate their next-generation SoCs against real-world devices months before silicon, reducing time-to-market and catching integration issues that simulation cannot find.
You will deliver Speed Adapter solutions that become the reference standard for In-Circuit Emulation and system-level validation workflows across the industry.
You will influence the adoption and implementation of emerging protocols like PCIe Gen7, CXL 4.0, and UCIe by building the tools that make early validation possible.
You will reduce customer bring-up time from weeks to days by delivering robust, well-documented adapter solutions that work out of the box.
You will shape the technical direction of Synopsys' hardware-assisted verification strategy, bridging IP, emulation, and prototyping into a unified system-level validation platform.
You will contribute to patent-pending technologies that differentiate Synopsys Speed Adapter solutions from competitive offerings and create measurable value for customers.
You will build the validation infrastructure that helps customers catch critical bugs in PCIe, CXL, and UCIe implementations before they become silicon respins.
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