Create and define verification plans, for digital verification of Mixed Signal designs Create new and improve existing verification environments in SystemVerilog language using Universal Verification Methodology (UVM) and Constrained Random approach Execute tests in these environments on RTL and gate-level and debug issues in design and verification environments Lead and coordinate other verification engineers in projects Closely cooperate with analog and digital designers as well as concept and other verification engineers Mentoring of junior colleagues, consultants and students Contribute to enhancement of existing methodologies and flows, by driving required innovation projects You work conscientiously on making things better, faster, and more efficient and keep up high quality standards for yourself and other people. You can solve technical problems and work independently. You are a team player and support your colleagues for the overall team and company success. A university degree in Electrical Engineering, Computer Science, Information Technology or a similar academic discipline 6+ years of experience in Digital Verification. as a plus Excellent know-how in SystemVerilog, UVM, and verification tools: Xcelium, Verdi and vManager or similar knowledge of RTL design (HDL) and digital or mixed-signal circuits knowledge of GIT, Python, and other programming languages as a plus We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills.
