What you'll do
You'll implement unified test plans for HPC DSP-based SERDES PHY products, integrating verification and validation phases in a structured workflow. You'll build and maintain robust verification environments using UVM methodology and SystemVerilog, including VIP integration. You'll develop, optimize, and share automation scripts (Shell, Perl, Python, C++, AI-based approaches) to support design, verification, and testing.
What you need
You'll need 10+ years of ASIC development and mixed-signal verification experience. You'll have expertise in PCIe, Ethernet protocols, and digital signal processing. You'll have advanced skills in SystemVerilog and UVM methodology for verification environment implementation. You'll be proficient in scripting (Shell, Perl, Python, C++); experience with AI-driven automation is a plus.
Why this matters
You'll directly influence the implementation and quality of flagship silicon IP products. You'll accelerate time-to-market for high-performance SoCs through effective testplan execution. You'll advance innovation in data recovery and signal processing, impacting global standards. You'll provide technical leadership and mentorship, supporting global customer success. You'll contribute to a knowledge-sharing, inclusive engineering culture.
