What you'll do
You'll be responsible for defining, documenting, and reviewing algorithms for SerDes PHY functions, with a focus on firmware and RTL implementation quality. You'll collaborate closely with architecture, analog, digital, firmware, and hardware teams to ensure the correctness and repeatability of SerDes algorithms across multiple protocols and standards.
- Defining, documenting, and reviewing algorithms for SerDes PHY functions, with a focus on firmware and RTL implementation quality.
- Collaborating closely with architecture, analog, digital, firmware, and hardware teams to ensure the correctness and repeatability of SerDes algorithms across multiple protocols and standards.
- Coordinating feasibility and robustness studies for new algorithmic features in high-speed serial protocols such as Ethernet and PCIe.
- Driving cross-team integration and validation to guarantee deterministic accuracy and stability from simulation through hardware demonstration, including thorough corner-case and stress testing.
- Analyzing lab and field data to refine, debug, and enhance algorithm performance, resilience, and repeatability.
- Supporting system-level debug, root cause analysis, and escalations related to algorithm implementation in firmware or RTL.
- Mentoring and guiding junior team members in the development and validation of algorithms, fostering growth and knowledge sharing across the team.
What you need
- MSc+ in Electrical/Computer Engineering or related field.
- 8+ years in algorithm/signal processing for SerDes PHY or mixed-signal systems.
- MATLAB/Simulink, C, or Python expertise.
- Hands-on SerDes modeling and calibration experience.
- Strong troubleshooting and cross-team collaboration skills.
Why this matters
- Advance next-gen 224G/448G SerDes PHY performance and reliability.
- Deliver robust, high-quality calibration and adaptation features and overall PHY performance.
- Drive successful implementation, verification, and validation of algorithmic features across multidisciplinary engineering teams.
- Enhance technical excellence and knowledge sharing.
- Strengthen Synopsys' leadership in high-speed PHY IP.
