Design the architecture of advanced testbenches using SV/UVM MS with 12+ years / BS with 14+ years Candidate should have strong background in digital verification usingSystem Verilog and UVM. Should have developed multiple verificationenvironments for complex IP's and SoC's. Should be capable ofdefining verification architecture for new IP's and should havedeveloped verification environments. Candidate should have worked on ARMbased SoC verification covering RTL, Power Aware and Gate levelsimulations. Exposure to deployment of automation and formalverification methodologies is a plus. We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.
