Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
These engineers play a crucial role in advancing technology and enabling innovations in various industries.
You have spent years deep in the physics of silicon, designing circuits that live at the boundary between analog behavior and digital logic. You know that a flip flop is not just a schematic, it is a careful negotiation between setup time, hold time, leakage, and clock load, and you have learned to make those tradeoffs without losing sleep or performance.
The difference between a cell that works in simulation and one that works in production across voltage corners, temperature swings, and process variation is something you have debugged enough times to see coming three steps ahead.
You are comfortable moving between SPICE simulations, post-layout extraction flows, and Python scripting to automate the parts that should not require manual intervention. Latch-up rules, electromigration limits, and design rule decks are not obstacles, they are constraints you design within, and you know how to push back when a spec does not make sense.
You care about PPA because you have seen what happens when power or area gets ignored until tapeout, and you would rather catch it now. At Synopsys, you will work on standard cells that go into libraries used across the industry, and the circuits you design will matter at scale.
Design and develop high-performance standard cells including flip flops, latches, multibit flip flops, voltage level shifters, power switches, clock buffers, and complex sequential logic.
Build and refine post-layout extraction environments to validate circuit performance against parasitic effects and real-world operating conditions.
Optimize digital and analog circuit topologies for power, performance, and area across multiple process nodes and operating corners.
Perform statistical and variation analysis using Monte Carlo and corner-based methods to ensure robustness across manufacturing spread.
Apply deep knowledge of CMOS device physics, design rules, latch-up prevention, and electromigration constraints to ensure reliable, manufacturable designs.
Collaborate with layout teams to close timing, power, and area targets while maintaining design intent through the physical implementation flow.
Automate repetitive design and analysis tasks using Python, shell scripting, or ICV to improve team efficiency and design consistency.
Your standard cell designs will be integrated into Synopsys IP libraries used by customers building chips for AI, automotive, mobile, and high-performance computing applications.
Improvements you make in flip flop performance or leakage will directly influence the power and speed of chips designed by leading semiconductor companies worldwide.
Your work on power optimization cells and level shifters will enable more energy-efficient SoCs, contributing to longer battery life and lower operating costs.
The robustness and variation tolerance you build into your designs will reduce yield loss and improve manufacturing success rates for our customers.
Collaboration across design, layout, and characterization teams will accelerate library development cycles and improve time-to-market for new process nodes.
Your contributions to automation and methodology will raise the quality bar for the entire standard cell design team.
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