Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.
As a Sr. Staff R&D Engineer, Analog design, you will develop, debug and maintain analog design flow based on extraction, simulation and EMIR flows and support project specific design environments for analog design circuit development across global foundation IP R&D team. You will also debug complex design issues spanning physical verification (DRC/LVS), extraction, simulation, and reliability analysis using Synopsys EDA tools like StarRc, ICV, Hspice, and Customsim, CustomCompiler etc.
You will build Python, TCL, and shell-based automation to eliminate manual steps and accelerate design cycles. You will configure and support IP project environments including Perforce data management and LSF job scheduling. You will collaborate directly with design teams to diagnose bottlenecks and deliver solutions that work for them.
Your work will reduce cycle time by automating flows that currently require manual intervention. Your debugging work will unblock critical design milestones, keeping tape out schedules on track across global projects. Your automation will eliminate entire categories of errors, improving first-pass success rates for verification runs. You will shape how new EDA tools get adopted with AI features, ensuring there is smooth integration.
You will be part of the Silicon Design & Verification business, the design enablement team building solutions for designing and verifying advanced silicon chips. This R&D group provides EDA tools, processes, and models support that help customers optimize chips for power, cost, and performance while cutting months off project schedules.
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