Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
In this role, you will work on the design, development, and refinement of Multi-Gbps NRZ & PAM4 SERDES IP. You will be part of a fast-growing analog and mixed signal R&D team developing high speed (>200Gbps) analog integrated circuits in the latest FinFET process nodes.
As an accomplished analog design engineer, you will thrive on solving complex technical challenges and collaborate with cross-functional teams to deliver best-in-class silicon solutions. Your expertise in SerDes and high-speed analog circuit design will be complemented by your hands-on experience in developing, verifying, and optimizing circuits for high performance, low power, and minimal area.
Responsibilities:
- Ownership of Analog Macro level design
- Tracking and reviewing the work of sub-block owners
- Review SerDes standards and architecture documents to develop analog specifications
- Identify and refine circuit implementations to achieve optimal power, area and performance targets.
- Propose design and verification strategies that efficiently use simulator features to ensure highest quality design.
- Oversee physical layout to minimize the effect of parasitics, device stress, and process variation.
- Collaborate with digital RTL engineers on the development of calibration, adaptation and control algorithms for analog circuits.
- Present simulation data for peer and customer review.
- Mentor and review the progress of junior engineers.
- Document design features and test plans.
- Consult on the electrical characterization of your circuit within the SerDes IP product.
Requirements:
- Advanced degree with 4+ years of SerDes/High-Speed analog design experience.
- In-depth familiarity with transistor level circuit design - sound CMOS design fundamentals.
- Silicon-proven experience implementing circuits for the TX, RX and Clock paths within a SerDes
- Experience in leading a small team of designers collaborating on building blocks of a Macro level design
- Detailed design experience with several of the following SerDes sub-circuits:
receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference, ADC, DAC
- Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects.
- Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.).
- Experience with EDA tools for schematic entry, physical layout, and design verification.
- Knowledge of SPICE simulators and simulation methods.
- Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
- Experience with TCL, Perl, C, Python, MATLAB.
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