Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
You are a passionate and inventive analog circuit design engineer with a deep-rooted curiosity for emerging technologies and industry-leading semiconductor processes. You thrive in dynamic, collaborative environments and are recognised for your ability to balance technical depth with practical implementation. Your expertise in I/O development, ESD (Electrostatic Discharge), and Latch-Up (LU) robustness sets you apart, and you are eager to build solutions that power the next generation of high-performance chips.
You bring a strong foundation in FinFet, FDSOI, and BCD technologies, and you are excited by the prospect of owning projects end-to-end,from conceptual design through to silicon qualification. Your approach is meticulous and data-driven, ensuring each design meets the highest standards of quality and reliability. You are comfortable working across cross-functional teams, collaborating with foundries, and integrating feedback from global stakeholders.
Continuous learning excites you, and you embrace opportunities to mentor others, share knowledge, and contribute to a culture of technical excellence. You are motivated by the impact your designs have on real-world products and are committed to delivering robust, scalable, and innovative solutions for Synopsys' worldwide customers.
You will design and develop best-in-class ESD and Latch-Up robust solutions for advanced interface IPs using cutting-edge FinFet, FDSOI, and BCD processes. You will own the full lifecycle of ESD structures,from schematic design, simulation, and layout to silicon qualification and production release. You will lead and execute I/O development, including I/O ring design, review, and optimisation for performance and robustness.
You will develop and qualify Interface Testchips, ensuring comprehensive ESD and Latch-Up validation to meet global customer requirements. You will run ESD simulations by building detailed ESD networks and performing advanced analyses to ensure design integrity. You will apply foundry-provided PERC (Physical Verification Rule Check) rules and use PERC check tools to validate compliance and enhance design quality.
You will collaborate closely with foundry partners, design, and layout teams to ensure timely and effective integration of ESD and LU solutions.
You will elevate the reliability and performance of Synopsys' interface IPs, directly influencing the success of global semiconductor customers. You will drive innovation in analog circuit design for next-generation silicon technologies, helping Synopsys maintain its leadership in the industry. You will reduce field failures and increase product longevity by delivering robust ESD and Latch-Up protection solutions.
You will accelerate time-to-market for customer products through efficient and high-quality design practices. You will foster a culture of technical excellence and continuous improvement within the analog design team. You will build strong partnerships with foundries and cross-functional teams, enhancing collaboration and knowledge sharing across projects.
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