Responsible for leading Physical Design and Timing Closure of low power SoCs. Enable next generation of place and route engineers via mentoring and thought leadership. Hands-on experience in physical design implementation and timing closure of large blocks/top Expert user of industry standard tools for physical design and signoff. Expert in scripting languages (shell, perl, tcl) and Make flow In-depth knowledge of 28nm/16nm/12nm technologies and associated physical design challenges Deep understanding of low power design techniques and implementation methodologies Should be self-motivated and take initiatives to drive new methodologies Should have strong written and verbal communication skills We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills.
