Responsible for SoC DFT Architecture definition/implementation/verification/silicon debug of SoC/Full Chip. Responsible for SoC DFT Architecture definition/implementation/verification/silicon debug of SoC/Full Chip. Responsible for ATPG, DRC analysis, Test coverage debug, Memory BIST implementation and verification. ASIC flow understanding. Experienced in LEC, CLP, power analysis flow is preferred The ability to work as an individual and as part of a team to deliver complex SoCs starting from the creation of the DFT spec, implementation, verification, and Post silicon debug. In addition, be self-motivated with the initiative to seek constant improvements in the DFT design methodologies. The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment. Scripting skills such as PERL/TCL/Python are preferred. 12+ years of in DFT implementation, verification and post silicon debug areas. We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills.
