Opening. Our team is looking for a skilled ASIC Digital Design Engineer to join our team in Ho Chi Minh City.
What you'll do
- Working in a Digital and Verification Development team during the development and validation of complex digital mixed signals for high-speed interface IP.
- Planning tests, checklists, coverage, and assertion planning.
- Creating detailed verification environments from functional specifications.
- Applying advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification.
- Writing test cases, checkers, and coverage that implement the verification test plan.
- Debugging simulations, including those of real signals modeled using SystemVerilog for analog.
- Performing RTL, GLS, and co-simulations and ensuring coverage closure.
- Participating in technical reviews and contributing actively.
- Providing customer support with the bring-up of IP in customer simulation environments.
- Following and improving development processes to ensure high-quality output.
What you need
- BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications.
- 8+ years of experience in design verification.
- Strong skills with VCS/Verdi simulation tools and formal verification tools (vc_formal).
- Knowledge of UPF, UVM (Universal Verification Methodology), and SVA (SystemVerilog Assertion) is a plus.
- Proficiency in debugging and demonstrated experience in Perl/TCL/Python scripting is a plus.
