What you'll do
You are an experienced verification engineer (3–8 years) passionate about developing reliable and robust SoC and ASIC solutions. You thrive in collaborative environments, are skilled with SystemVerilog (UVM preferred), and enjoy tackling complex debugging and coverage challenges. You automate workflows with scripting (Perl, Tcl, csh, or Python) and communicate clearly in a dynamic team. You’re detail-oriented, proactive, and eager to contribute to advanced chip development.
What you'll be doing:
- Develop reusable verification environments and testbenches using UVM.
- Plan, maintain, and execute verification strategies for ASIC/SoC projects.
- Create test cases, set up and run regressions, and close coverage.
- Debug daily regressions and document all activities.
- Lead review meetings with design and verification teams.
- Automate tasks and improve verification flows with scripting.
What you need:
- Minimum 6 years’ SoC/ASIC verification experience.
- Strong SystemVerilog (UVM preferred) skills.
- Expertise in assertions-based and constraint random verification.
- Experience with coverage-driven verification and HVP.
- Scripting skills: Perl, Tcl, csh, or Python.
- Familiarity with VCS and Verdi tools.
Who you are:
- Collaborative and proactive team player.
- Strong communicator and problem solver.
- Detail-oriented and organized.
- Adaptable and willing to learn.
The team you’ll be a part of:
Join a collaborative, innovative team of digital design and verification engineers in Ho Chi Minh City, delivering high-quality semiconductor solutions for global customers.
