What you'll do
You'll be designing and implementing digital ASIC blocks for LPDDR6/DDR IP.
- Writing and verifying RTL code (Verilog/SystemVerilog).
- Running lint, CDC, DFT, and synthesis checks.
- Debugging simulation and silicon issues.
- Using Synopsys EDA tools: VCS, Verdi, Spyglass, DC, Formality.
- Collaborating with design, verification, and customer teams.
What you need
You'll need:
- BSEE + 5 years or MSEE + 3 years in digital design.
- Strong RTL coding (Verilog/SystemVerilog) skills.
- Debugging expertise for simulation/silicon.
- Experience with Synopsys EDA tools.
- Knowledge of lint, CDC, DFT, synthesis flows.
Why this matters
You'll advance next-generation memory IP for global applications.
What You'll Be Doing
Designing and implementing digital ASIC blocks for LPDDR6/DDR IP.
What You'll Need
BSEE + 5 years or MSEE + 3 years in digital design.
The Impact You Will Have
Advance next-generation memory IP for global applications.
The Team You'll Be A Part Of
Join a diverse, expert team focused on LPDDR6 and next-gen memory IP, where collaboration and technical excellence drive success.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.
