What this role is and why it exists.
This role exists to develop comprehensive test plans for formal verification tools and innovative methodologies.
What you'll do
- Develop comprehensive test plans for formal verification tools and innovative methodologies.
- Validate advanced features of EDA tools such as Synopsys VC Formal, including Property Verification (FPV), Sequential Equivalence (SEQ), and Connectivity Checking.
- Create and execute robust test cases and regression suites to thoroughly assess tool functionality and performance.
- Analyze tool behavior, debug complex issues, and effectively communicate findings to the R&D team for resolution and improvement.
- Collaborate closely with cross-functional teams, including R&D, application engineers, and product management, to define and enhance tool features.
What you need
- Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related discipline.
- 2–14 years of experience in formal verification or EDA tool validation.
- Hands-on experience with formal verification tools such as Synopsys VC Formal.
- Strong knowledge of formal methods, SystemVerilog Assertions (SVA), and digital design fundamentals.
- Proficiency in scripting languages (Python, Perl, Tcl) within Unix/Linux environments.
Why this matters
- Ensure the reliability and performance of industry-leading formal verification tools used globally in chip design.
- Drive quality improvements that directly influence customer success and satisfaction.
- Contribute to faster time-to-market for advanced silicon solutions by validating and enhancing verification tool capabilities.
- Empower cross-functional teams with actionable insights and feedback that shape product direction and innovation.
- Advance the state-of-the-art in formal verification methodologies, helping Synopsys maintain its leadership position.
