Must have worked in ASIC Design flow, with ASIC experience of upto 5years. Must be strong in scripting using Perl/Python Must be familiar with RTL design for ASIC development using Verilog. Must be familiar with LINT (LEDA/Spyglass),Clock-Domain-Crossing analysis, UPF, MVRC, Synthesis, Timing constraints and debugging STA reports. Strong mindset towards automation of repetitive work. Strong fundamentals in DFT/Fault-grading and/or hands on experience. Sound & Practical Written and Verbal Communication Skills. Moderate Individual Contributor with Freedom to Act, Team work and Learn We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills.