develop verification environments for our ICs using UniversalVerification Methodology (UVM). develop assertions in SystemVerilog for formal verification; provide proactive support to users of our verification flowenvironment; You have successfully completed a university degree in Electrical Engineering, Computer Science or a similar academic discipline; You have at least 3 years of experience in Constrained-Random Metric-Driven Verification You have capabilities and experience in working with microcontroller-based ICs, as well as security and safety requirements; You have good know-how with UVM especially using SystemVerilog. Have knowledge of firmware and RTL design (VHDL); Ideally have knowledge of working with Verification IPs (VIPs) We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.