You will work on tools that define power integrity and reliability signoff for the most advanced semiconductor nodes shipping today.
Design, develop, and optimize core algorithms for the Totem product line, focusing on power noise integrity, electromigration, thermal analysis, and electrostatic discharge modeling for advanced nodes including 3DIC, FinFET, and GAA architectures.
Build and maintain high-performance C++ code that handles parasitic extraction, transistor-level simulation, and gate-level power analysis across distributed processing environments.
Diagnose and resolve complex software defects in large-scale commercial codebases, ensuring correctness, scalability, and maintainability under tight delivery schedules.
Optimize tool runtime and memory capacity for designs with billions of transistors, using profiling, parallel processing techniques, and algorithmic improvements.
Create unit, regression, and system-level tests that validate new features and changes across the full product stack.
Collaborate with technical leads, product management, and field engineers to refine solutions based on customer design challenges at 3nm and beyond.
Explore and integrate machine learning and AI techniques to improve accuracy, performance, and predictive capabilities in EDA workflows.
Your code will directly enable signoff accuracy for power and reliability analysis on the most complex ICs shipping in smartphones, data centers, and AI accelerators.
Performance improvements you deliver will reduce analysis runtime by hours or days, helping customers meet aggressive tapeout schedules.
The algorithms you build will help semiconductor companies navigate the physics challenges of sub-3nm nodes, FinFET, GAA, and 3DIC stacking.
Your optimization work will expand the capacity of Totem tools, allowing analysis of larger designs without requiring customers to partition or compromise accuracy.
Test frameworks you create will catch regressions before they reach customers, protecting product quality and customer trust.
Your collaboration with field teams will translate real-world design pain points into software improvements that matter.
Machine learning techniques you integrate will position Synopsys tools at the leading edge of AI-driven semiconductor analysis.
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