Our team at Synopsys is seeking an IP (PCIE/CXL/USB/DP) Subsystem Design Implementation Engineer to join our team. As a key member of our design implementation team, you will be responsible for designing and implementing high-speed interface IP subsystems for various applications, including AI acceleration, GPGPU, and Big-Data SOC chips.
Key qualifications:
- Minimum 5+ years of experience in IP/ASIC/SOC design implementation
- Hands-on experience in synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.
- Domain understanding of one of the interface standards: PCIe, USB, Display Port, Ethernet, or DDR
- Good communication skills while interacting with internal teams and customers
Preferred Experience:
- Experience in Design Compiler, Fusion Compiler, PrimeTime, Spyglass, or VC Spyglass
- Experience in DesignWare Core IPs or PHYs
- Experience in TCL, Perl, Python, or other shell scripting
As a member of our team, you will have the opportunity to work on cutting-edge projects and collaborate with experienced engineers. You will also have access to state-of-the-art tools and technologies, as well as opportunities for professional growth and development.
Benefits:
- Comprehensive medical and healthcare plans
- Time away programs (ETO and FTO)
- Family support (maternity and paternity leave, parenting resources, adoption and surrogacy assistance)
- ESPP (purchase Synopsys common stock at a 15% discount)
- Retirement plans
- Competitive salaries
If you are a motivated and experienced engineer looking for a new challenge, please submit your application.
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