You will shape the next generation of memory IP that powers everything from AI accelerators to automotive SoCs.
As a Senior Architect in our Memory Compiler Design team, you will be responsible for architecting and developing memory compiler IP across SRAM, register file, ROM, and TCAM technologies. You will own the full flow from circuit design through functional verification and signoff.
Key responsibilities include:
- Architecting and developing memory compiler IP
- Designing and optimizing analog circuits at the transistor level using Hspice/XA
- Building and refining memory compiler flows using Python
- Collaborating with product engineering, verification, and customer support teams
- Driving functional verification using industry-standard tools
- Mentoring engineers across circuit design, memory architecture, and compiler methodology
The ideal candidate will have 20+ years of hands-on experience designing embedded memory IP, including SRAM, register files, ROM, or TCAM, with deep expertise in circuit-level design and functional verification. You will also have strong proficiency in Python for scripting, automation, and flow development, as well as expert-level skill in Hspice or XA for analog circuit simulation, optimization, and characterization.
If you are a motivated and experienced engineer looking to join a dynamic and innovative team, please apply now.
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