Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
This role requires a deep understanding of SerDes technology, including optical specs, SerDes modeling in MATLAB/Simulink, high-speed analog CMOS design, DSP for SerDes, and communications theory.
As a SerDes Optical System Architect, you will work on SerDes IP powering PCIe Gen6+ and 200G+ Ethernet in optical systems that ship. The team is deep, the problems are hard, and what you architect matters.
Key responsibilities include building and maintaining SerDes system models in MATLAB/Simulink for NRZ and PAM4 optical links, running sign-off simulations across PCIe 128Gbps+ and Ethernet 200Gbps+ protocols to verify performance, designing calibration and adaptation algorithms to tune transceiver performance, correlating simulation with silicon measurements and iterating models, supporting customers on system-level performance and optical integration issues, and working with analog, digital, and hardware teams across all development stages.
The impact you will have includes defining what gets built, catching issues before silicon respins, shaping SerDes IP performance for hyperscale data centers, AI infrastructure, and next-generation networking, enabling real-time adaptation, improving yield and margin, closing the simulation-to-silicon gap, reducing customer debug cycles, informing next-generation architecture, helping Synopsys maintain leadership in high-speed optical SerDes, and mentoring engineers across analog, digital, and system domains.
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