Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
As a Senior ASIC Digital Design Engineer, you will be responsible for architecting and developing RTL for high-bandwidth PHY IP and test chips. You will define synthesis constraints, resolve STA and simulation issues, and collaborate with verification, controller, and lab teams.
Key responsibilities include:
- Performing logical and physical synthesis, formal verification, and quality checks
- Analyzing timing violations and generating reports
- Mentoring junior engineers and supporting digital flow development
The impact you will have as a Senior ASIC Digital Design Engineer includes enabling innovative IP solutions for global customers, improving product reliability and efficiency, accelerating development cycles with strong teamwork, and resolving customer technical challenges.
To be successful in this role, you will need to have a BS/MS/PhD in Electronics Engineering or a related field, with 2-6+ years of RTL design and synthesis experience. You should be an expert in industry tools (VCS, Verdi, Spyglass, Synopsys sign-off) and have strong scripting skills (Perl, tcl, Python, Shell).
You will be a responsible, result-oriented, and proactive individual who is enthusiastic about technology and problem-solving. You will be a collaborative and clear communicator, adaptable, and willing to mentor others.
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