Opening. This role is part of the R&D team at Synopsys, working on developing and maintaining software used in chip design, verification and manufacturing. The team is responsible for creating highly optimized hardware IP for the ARC family of configurable processors.
What you'll do
- Develop and maintain microprocessor hardware IP including specification, implementation, verification, and FPGA validation, with an emphasis on validating system architecture and performance for DSP processor IP or Neural Processing Unit (NPU) IP.
- Optimize designs for performance, area, and power efficiency.
- Create and enhance tests for hardware IP verification and validation, improving functional coverage and performance through the application of state-of-the-art methodologies.
- Collaborate with global teams in tools, modeling, and simulation to deliver optimized solutions for our customers.
What you need
- Passion for embedded processors or processor-based systems.
- Knowledge of HDL design, preferably in RISC processor architectures, DSP, AI (NPU), and multi-core systems.
- Familiarity with Verilog and SystemVerilog.
- Experience with RTL simulation tools (e.g., VCS).
- Scripting or programming skills in assembler, C, Tcl, Csh, or Python.
- Experience with embedded software for DSP or AI reference models is a plus.
Why this matters
- Contribute to the development of highly optimized hardware IP for the ARC family of configurable processors.
- Enable customers to create sophisticated and efficient embedded designs.
- Support the delivery of world-class microprocessors used in advanced applications.
- Help improve functional coverage and performance of processor IP through advanced verification methods.
- Collaborate globally to deliver customer-focused solutions.
- Drive continuous improvement in processor system verification.
What you’ll be doing
- Develop and maintain microprocessor hardware IP including specification, implementation, verification, and FPGA validation, with an emphasis on validating system architecture and performance for DSP processor IP or Neural Processing Unit (NPU) IP.
- Optimize designs for performance, area, and power efficiency.
- Create and enhance tests for hardware IP verification and validation, improving functional coverage and performance through the application of state-of-the-art methodologies.
- Collaborate with global teams in tools, modeling, and simulation to deliver optimized solutions for our customers.
What you’ll need
- Passion for embedded processors or processor-based systems.
- Knowledge of HDL design, preferably in RISC processor architectures, DSP, AI (NPU), and multi-core systems.
- Familiarity with Verilog and SystemVerilog.
- Experience with RTL simulation tools (e.g., VCS).
- Scripting or programming skills in assembler, C, Tcl, Csh, or Python.
- Experience with embedded software for DSP or AI reference models is a plus.
Why this matters
- Contribute to the development of highly optimized hardware IP for the ARC family of configurable processors.
- Enable customers to create sophisticated and efficient embedded designs.
- Support the delivery of world-class microprocessors used in advanced applications.
- Help improve functional coverage and performance of processor IP through advanced verification methods.
- Collaborate globally to deliver customer-focused solutions.
- Drive continuous improvement in processor system verification.
