Accelerate deployment and adoption of Synopsys Verification IP, directly contributing to customer project success and market leadership.
What you'll do
- Lead the integration and deployment of Synopsys Verification IP at strategic semiconductor accounts, driving seamless adoption in simulation, emulation, and hybrid environments.
- Own evaluation cycles, competitive displacements, and “first bring-up” engagements, ensuring customer success throughout the process.
- Define end-to-end verification strategies for complex SoCs, focusing on coherency, interconnect behavior, performance validation, and subsystem-level flows.
- Provide architectural guidance on VIP and IP flows, including Arm-based architectures and advanced protocols (PCIe/CXL, DDR/LP, UFS/USB).
- Serve as the expert escalation point for complex system-level debug issues, coordinating cross-functional teams (AE, PMG, R&D) to resolve challenges.
- Develop and maintain reusable collateral such as test suites, protocol compliance documents, debug guides, and integration documentation aligned with industry standards and customer expectations.
- Partner with R&D, PMG, and Sales to drive feature delivery, roadmap planning, bug triage, and methodology improvements.
- Deliver customer workshops, deep-dive technical sessions, and internal enablement programs, representing Synopsys at conferences and protocol working groups as needed.
What you need
- Expertise in UVM, SystemVerilog, and VIP development/integration in simulation and emulation environments.
- Deep understanding of advanced protocol standards, including PCIe/CXL, DDR/LP, UFS/USB, and related interconnects.
- Hands-on proficiency with debug tools (e.g., Verdi), performance analysis, and coverage closure methodologies.
- Strong programming skills in SystemVerilog, UVM, Verilog, C/C++, and Python.
- Experience with industry-standard tools such as VCS, Verdi, Specman, and Jira.
- Familiarity with subsystem verification, native UVM/SV flows, and protocol compliance strategies.
