You are a passionate engineer with a keen interest in the intricate world of formal verification and EDA tool validation. You thrive on solving complex technical problems and are motivated by the challenge of ensuring the highest standards for cutting-edge verification solutions.
What you'll do
Develop comprehensive test plans for formal verification tools and innovative methodologies.
- Validate advanced features of EDA tools such as Synopsys VC Formal, including Property Verification (FPV), Sequential Equivalence (SEQ), and Connectivity Checking.
- Create and execute robust test cases and regression suites to thoroughly assess tool functionality and performance.
- Analyze tool behaviour, debug complex issues, and effectively communicate findings to the R&D team for resolution and improvement.
- Collaborate closely with cross-functional teams, including R&D, application engineers, and product management, to define and enhance tool features.
- Stay current with the latest formal verification methodologies, industry standards, and emerging trends to drive innovation in tool development.
What you need
- Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related discipline.
- 8+ years of experience in formal verification or EDA tool validation.
- Hands-on experience with formal verification tools such as Synopsys VC Formal.
- Strong knowledge of formal methods, SystemVerilog Assertions (SVA), and digital design fundamentals.
- Proficiency in scripting languages (Python, Perl, Tcl) within Unix/Linux environments.
