You are a skilled digital design engineer with strong ASIC experience and a passion for innovation. You bring at least 5 years (BSEE) or 3 years (MSEE) of hands-on digital design, with a solid grasp of RTL coding (Verilog/SystemVerilog), and a knack for debugging both simulation and silicon issues. You’re comfortable with Synopsys EDA tools, thrive in collaborative environments, and communicate clearly across teams. You’re curious, eager to learn new technologies, and have an interest in DDR/LPDDR, HBM, or UCIe. Scripting skills and analog circuit knowledge are a plus. You’re driven, detail-oriented, and ready to contribute to advanced memory IP design.
What you'll do
Designing and implementing digital ASIC blocks for LPDDR6/DDR IP.
Writing and verifying RTL code (Verilog/SystemVerilog).
Running lint, CDC, DFT, and synthesis checks.
Debugging simulation and silicon issues.
Using Synopsys EDA tools: VCS, Verdi, Spyglass, DC, Formality.
Collaborating with design, verification, and customer teams.
What you need
BSEE + 5 years or MSEE + 3 years in digital design.
Strong RTL coding (Verilog/SystemVerilog) skills.
Debugging expertise for simulation/silicon.
Experience with Synopsys EDA tools.
Knowledge of lint, CDC, DFT, synthesis flows.
