We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.
You Are:
You are a highly driven engineering professional with a passion for solving complex problems in the verification domain. With a strong foundation in digital design, HDL/HVL languages, and verification methodologies, you thrive in environments that challenge your technical acumen and reward your innovative mindset. You are eager to stay ahead of industry trends, exploring AI-driven productivity tools and advanced simulation technologies to deliver robust solutions. Your communication skills are exceptional, enabling you to collaborate seamlessly with global teams and articulate technical concepts to diverse audiences.
What you'll do
Lead customer deployments of VCS simulation technology, working closely with field teams and R&D to ensure successful adoption and integration.
Diagnose and troubleshoot complex technical issues in verification flows, utilizing deep product knowledge and analytical skills.
Collaborate with global domain experts to gather requirements and contribute to the development of a robust product roadmap.
Drive competitive engagements by demonstrating Synopsys VCS advantages and supporting customers in benchmarking scenarios.
Provide technical expertise in HDL/HVL methodologies, including UVM, SVA, and simulation debugging.
Interface directly with customers, product validation, and R&D teams to propose solutions and suggest improvements in implementation and validation processes.
Develop and optimize scripts (Perl, TCL, Shell, Make) to enhance productivity and workflow automation.
What you need
Bachelor’s degree in Electronics with 7+ years or Master’s degree in Electronics with 5+ years of experience.
Proficiency in verification technologies, including simulation, UVM, SVA, and LRM.
Strong expertise in HDL languages (Verilog, VHDL, SystemVerilog) and digital design fundamentals.
Proven experience in debugging simulation mismatches and verification flows.
Advanced scripting skills (Perl, TCL, Make, Shell) and working knowledge of UNIX environments.
Exposure to Synopsys EDA tools such as SpyGlass, VC SpyGlass, Verdi is a plus.
