As a Verification Engineer at Synopsys, you will be responsible for designing and implementing self-checking test benches using modern verification techniques. You will develop verification components such as bus functional models, monitors, and behavioral models. Your expertise in implementing functional coverage and assertions using System Verilog is unmatched. You will be a problem-solver who thrives in debugging simulation failures and analyzing functional coverage results. Your strong Verilog coding skills, combined with your prowess in C/C++ or Python scripting, make you a valuable asset to any team.
What you'll do
- Designing and implementing self-checking test benches using modern verification techniques.
- Developing verification components such as bus functional models, monitors, and behavioral models.
What you need
- Expertise in System Verilog and functional coverage.
- Strong Verilog coding skills.
- Proficiency in C/C++ or Python scripting.