You'll join the Mixed-Signal IP organization, a world-class team of engineers dedicated to developing advanced high-speed SerDes and mixed-signal IP across leading-edge process nodes. The team is renowned for technical innovation, close collaboration, and a relentless pursuit of excellence in delivering industry-defining solutions for Synopsys' global customers.
What you'll do
Managing the physical implementation of high-speed interface IPs and testchips, ensuring successful delivery across advanced process nodes.
- Driving cross-functional collaboration with analog, digital, CAD, and product teams to optimize flows and resolve design challenges.
What you need
12+ years of digital or physical design experience, including recent project tape-outs as a technical driver or project lead.
Deep knowledge of the full design cycle (RTL to GDSII) at the chip level, with experience in advanced FinFET nodes (TSMC 16nm or below).
Strong engineering foundation in digital architecture, implementation flows, and physical/timing signoff.