ASIC Digital Design Staff Engineer

Synopsys • Full-time • Ho Chi Minh City • 3h ago

You are a skilled digital design engineer with strong ASIC experience and a passion for innovation. You bring at least 5 years (BSEE) or 3 years (MSEE) of hands-on digital design, with a solid grasp of RTL coding (Verilog/SystemVerilog), and a knack for debugging both simulation and silicon issues.

What you'll do

Designing and implementing digital ASIC blocks for LPDDR6/DDR IP.

Writing and verifying RTL code (Verilog/SystemVerilog).
Running lint, CDC, DFT, and synthesis checks.
Debugging simulation and silicon issues.
Using Synopsys EDA tools: VCS, Verdi, Spyglass, DC, Formality.
Collaborating with design, verification, and customer teams.

What you need

BSEE + 5 years or MSEE + 3 years in digital design.

Strong RTL coding (Verilog/SystemVerilog) skills.
Debugging expertise for simulation/silicon.
Experience with Synopsys EDA tools.
Knowledge of lint, CDC, DFT, synthesis flows.

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