What you'll do
You'll be working on digital design for high-speed serial interface PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards.
- Proposing micro-architecture of design/design updates based on customer requirements, analog requirements, system performance improvements, Link layer interface changes, or overall robustness of design.
- Implementing RTL in Verilog and running Spyglass CDC/RDC/Lint.
- Collaborating with verification teams to test desired functionality and corner cases.
- Developing timing constraints, DFT insertion, and test coverage, and closing timing with physical design teams.
What you need
- 5-8 years of relevant experience in digital design for ASICs.
- Strong knowledge of Verilog RTL design and microarchitecture.
- Experience with timing constraints development and synthesis flow.
- Proficiency in using Spyglass or similar tools for Lint/CDC/RDC.
- Proficiency in scripting and automation using TCL, PERL, or Python.
Why this matters
- Enhancing the performance and reliability of high-speed serial interface PHY IPs.
- Contributing to the development of cutting-edge technologies that power modern electronics.
- Driving innovation in digital design and influencing the future of semiconductor technology.
- Collaborating with cross-functional teams to deliver robust and high-quality designs.
- Ensuring that Synopsys remains a leader in the semiconductor industry through continuous improvement and excellence.
Rewards and Benefits
- We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.
- Our total rewards include both monetary and non-monetary offerings.
- Your recruiter will provide more details about the salary range and benefits during the hiring process.
