What this role is and why it existsThis role exists to contribute to the verification (by creating digital design in HDL) of Formal EDA solutions.## What you'll doYou will contribute to the verification (by creating digital design in HDL) of Formal EDA solutions. The verification will involve understanding digital / RTL design, debug methodology and verification methodology. You will be involved in the complete chain of the EDA verification process, starting from defining the test specification, test case development and implementation, performance testing and giving feedback for improvement.- Grow into Formal Consulting role for major customers of Synopsys.- As part of the largest EDA Company, you will be in contact with remote teams on different continent.- Explore and integrate GenAI-based solutions into validation processes- Develop and implement automation techniques to enhance validation efficiency## What you needTo succeed in this role, you'll need:- BSc/MSc in the domain of Electronics/Electrical Engineering- 2 years of experience- Knowledge of digital design concepts- Expertise is one of the scripting languages Python or Perl or Shell- Knowledge of Verilog/VHDL- Familiarity/knowledge/experience with any of the following would be a plus: EDA/CAD tools, Simulation, Synthesis, Formal Verification, logic synthesis, DFT, FPGA/ASIC designs## Why this mattersEnable Synopsys’ customers to achieve first-time silicon success through robust verification and support. Enhance the quality, reliability, and performance of next-generation semiconductor products. Contribute to the development of scalable and reusable verification environments. Drive customer satisfaction by assisting in timely and effective technical solutions.
